From the archives: the origins of VirtuosoNext

VirtuosoNext Designer can be considered a 5th generation of the Virtuoso RTOS, whose origins go back to 1991. It was the first RTOS that was completely distributed and mainly used for parallel DSP applications, often in the demanding aero-space-defense domain. Some target systems had 12000 processors, the most prominent one was ESA's Rosetta spacecraft [1].

After Wind River acquired it and itself became part of Intel, Virtuoso lived on as VSPWorks, RocketRTOS and has now been adapted with almost no changes as Zephyr by the Linux community. At Altreonic, it was redeveloped from scratch in 2005 using formal modeling in the OpenComRTOS project. The latter was a milestone as it resulted in a much cleaner architecture using a generic "Hub" entity. The latter resulted in a code size that was up to ten times smaller than before. See the first attachment.

This history and experience is still very present in the current VirtuosoNext Designer that has been ported to many state of the art modern MP-SoCs. In addtion, it adds fine grain space and time partitioning but still applications will run mostly unmodified from lower end microcontrollers like the ARM-M3 to high-end Soc like the TI C6678 8-core DSP [2] and targets like ARM-A9 on OMAP4460 [3] and Freescale (now NXP) 7448 PowerPC [4].

Therefore, it is fun to find back one of the older publications on Virtuoso on Academia.edu [5]. The reader will notice the radical change in the architecture. While the original Virtuoso RTOS had actually a microkernel as well as an assembly written nanokernel, the latter makes no sense anymore on today's advanced processors. Latencies are now measured in nanoseconds without having to use assembler. Enjoy the papers in attachment.