DSP Valley has participated once again with a delegation of its members (Altreonic, Ansem, Byte Paradigm, NXP, Target Compilers) on the FIT (Flanders Investment & Trade organization) booth at the ESEC show in Tokyo. Given the dramatic earth quake and tsunami 2 months earlier, show attendance was somehow lower than the previous year but that was barely visible looking at the constant flow of visitors and did not result in less contacts.
Altreonic is engaged in a project thinking about (very) long life electronic devices. Practically speaking, long live means either they last a life time, either the device is used in environmental conditions subjecting it to accelerated ageing often due to agressive stress (vibration, chemical, radiation).
The project aims at researching novel approaches to develop resilient embedded programmable semiconductor devices with a very long life time, set at a symbolic goal of 100 years, even if some domains like bio-medical have already requirements spanning a lifetime of 70 to 80 years. A second domain is made up by applications where the devices are subjected to higher than normal stress resulting in a higher probability of failure. A third domain is focused on develiping consumer devices that have a much longer useful life than it is the case today.
This requires a holistic systems engineering approach, covering multiple domains such as system architecture, mechanical design, electro-chemical behaviour, software architecture, semiconductor technology and architecture, energy harvesting and non-functional aspects like long term reuse and maintainability. Application domains are diverse: infrastructure, transport systems, energy grids, bio-medical, consumer devices, aerospace and many other. The main goal is to make a significant step towards developing resilient high reliability devices in a cost-efficient way. We expect benefits that apply equally well to the current day engineering end development of high reliability systems, especially as the shrinking of the semiconductor elements is gradually eroding the robustness margins so that even at shorter lifetimes reliability becomes an issue.
The project will benefit from analysing typical use cases and applications where this is case. If interested to be part of the project or its user group, please contact us at long.live (@) altreonic.com
A recent article in EE-Times Europe states that computing has hit a power wall. Indeed, chip designers spoiled programmers in the past with ever increasing amount of compute cycles and memory space to waste. This has lead to great new features, which we all would like to keep, however the way we program these hardware monsters has not really changed. Yes compilers have become better in optimising code, but everything after has stayed the same. The linking phase of C / C++ programs is still largely a brute force operation, including everything the program might need and very often code that never will be executed. This leads to enormously bloated programs, that have to be a) stored in non-volatile storage, and b) in the RAM of the system that execute them. A simple “Hello World” might need a few Mbytes and links in 10000’s of functions. While this is less of a issue in desktop type systems, due to them having ample of cheap (D)RAM available and reasonably sized caches, the latter is not true for embedded systems, which represent the ever growing bulk of computer driven systems on the planet. Needing a lot of (D)RAM does not only cost money, but also energy, because (D)RAM needs to be continuously refreshed and operates often with 100’s of wait states compared with the superfast GHz CPUs. Thus this becomes part of the power wall we are currently hitting. And to follow Moore’s law, the only way forward is more parallel processing cores on the same die, even if that doesn’t increase the access speed to the external (D)RAM. In the end, chips are pin-bound. Performance is cache bound on such chips and therefore code size still matters.
Model-Driven Development Day 2011 29th April in Eindhoven.
Eric Verhulst, CEO/CTO of Altreonic will present "Beyond modeling: let the system meet the specifications."
Following the imminent release of the Springer book on OpenComRTOS, Altreonic has decided to now include the kernel source code and the build system with its licenses. Hence the binary license is dropped and replaced with the source code license. With v 1.4. also a new users manual was released coovering all integrated tools as well as the Safe Virtual Machine for C. The OpenTracer is now also available as a stand-alone tool.
Download the latest Win32 OpenComRTOS suite and the new manual from the download section. This is a unique opportunity to discover that parallel concurrent programming on large heterogenous networked processors, whether on a single chip or physically widely distributed, is not difficult at all. Provided the right paradigm is used from the very beginning. We call it "Interacting Entities".
Before this question can be answered, we need to refine the question. A simple answer could be that the lifetime of a processor is equal to its MTTF or Mean Time To Failure. This doesn't help us a lot because the MTTF is not a unique number. Leaving out the mean calculation, just like interrupt latency the Time To Failure is not a unique number. It is a histogram and the distribution will depend on the usage pattern.
The OpenComRTOS designer suite v.1.4. (Win32) with new supporting tools and demos is now avalable from the download section.
An interesting new example is the e-wheel simulator (see screenshot). It is composed of 3 nodes, one handling the input from the user, one running the control loop and one running the physical model. An additional windows application handles the 3D visualisation and user input. While the example is a simulation, it is complete and by a simple recompilation the controller node can be remapped to e.g. an attached ARM controller (of any other supported). This ewheel demo is also the subject of a Master Thesis proposal supported by Flanders Drive. Interested students can contact us or Flanders Drive. For details see the attached thesis outline.
Altreonic has finalised a description of the OpenComRTOS project in the form of a book to be published by Springer. It discusses the reasons behind the project, why and how formal methods were used, and how the results were beyond our initial expectations. Its title is:
"Formal Development of a Network-Centric RTOS: Software Engineering for Trustworthy Embedded Systems".
Before the book will be printed, we are looking at giving it a last polish based on the review of a few selected readers. If interested, please contact Eric (dot) Verhulst (at) Altreonic.com stating your motivation and credentials. The selected reviewers will receive a hard copy once the book is printed. Below the preface and the T.O.C.
As last year Altreonic will be exhibiting at the Embedded World exhibition and conference. Highlights are:
- OpenComRTOS 1.4 suite with unique support for distributed priority inheritance with resource management and the integrated Safe Virtual Machine for C.
- OpenCookBook v.2 in preview
- StarFish scalable and SIL3/4 capable controllers.
Besides integrated software tools and hardware controllers, Altreonic offers its expertise to customers looking for innovative solutions, in particular in the domain of low power and smart distributed or fault tolerant control.
Altreonic is also presenting at the Embedded World conference on Tuesday, March 1 at 1400. Dr Bernhard Sputh will present in session 05 (RTOS II) the paper “A safe virtual machine for C in less than 3 Kbytes”. A preview of the paper and the presentation is available from our website.
Altreonic is new releasing v.1.4 of its breakthrough formally developed network-centric OpenComRTOS suite. While the visual development environment was enhanced to make multi-processor developments even easier, v. 1.4 now has the Safe Virtual Machine (SVM) for C fully integrated and the RTOS itself has now fully distributed support for priority inheritance for easier resource management. The latter is a pre-condition for lower power consumption and better predictable real-time behaviour at the application level.